Flash memory is among one of the non-volatile memory devices that may retain its data at power-off. The flash memory device may be an electrically programmable and erasable device that does not need the refresh function of rewriting data at predetermined intervals. The term “program” refers to an operation of writing data into a memory cell and the term “erase” refers to an operation of erasing data written into a memory cell.
The flash memory device may be generally classified as a NOR type flash memory device and an NAND type flash memory device depending on a structure and operating condition of a cell. In the NOR type flash memory device, the drain of each memory cell transistor is connected to a bit line, which enables program and erase with respect to a specific address. The NOR type flash memory device has been generally used for applications requiring a high-speed operation. On the other hand, in the NAND type flash memory device, a plurality of memory cell transistors are connected in series, thus forming one string. The string may be connected to a bit line and a common source line. The NOR type flash memory device facilitates a higher level of integration and is therefore generally used for application fields requiring the retention of a high capacity data.
So far, there is a limitation to the reduction in the memory cell size of a highly integrated flash memory device due to patterning technology and process equipment. Increasing efforts have been devoted to find a viable technology for developing a multi-bit cell that is able to store plural data in one memory cell. The memory cell having this operating method is called a multi-level cell (MLC).
The MLC generally has two or more threshold voltage (Vt) distributions and two or more corresponding data storage states. For example, the MLC that is able to program 2-bit data may have four data storage states (i.e., [11], [10], [01] and [00]). The four data storage states correspond to threshold voltage distributions of the MLC, respectively. When a threshold voltage of the MLC corresponds to one of the four threshold voltage distributions, data information of 2 bits, which corresponds to one of [11], [10], [01] and [00], is read. The MLC having insufficient read margin may cause a drop in yield. It is therefore necessary to secure a sufficient read margin between the threshold voltage distributions in each level.
Further, high integration leads to reduction in the width and distance of devices. This results in a disturbance phenomenon between the devices, causing malfunctions of the devices. This is described below in connection with a program operation of a flash memory device.
The program operation may be performed by applying an increased threshold voltage to a word line in order to inject electrons into a floating gate. To this end, a program voltage is applied to a selected word line. As a plurality of memory cells are connected to the selected word line, the memory cells included in the unselected strings may be applied with the program voltage. Consequently, the program operation may be performed on memory cells. A channel boosting may be generated in the unselected strings by controlling the voltage of a select transistor and a bit line in order to prevent electrons from being introduced into the floating gate.
However, during channel boosting, a junction region between a source select transistor and an adjacent memory cell may boost to a specific voltage (for example, 8V) and the gate of the source select transistor is grounded. This corresponds to a condition in which a gate induced drain leakage (GIDL) may be generated at a portion where the source select transistor is overlapped with the junction. Electrons of electron-hole pairs generated at this portion may rapidly move to a channel region in which a high bias has been applied. Further, if the program voltage is applied to the word line nearest to the source select transistor, part of the electrons surpass the floating gate and an unwanted program operation may be carried out.